1. Field of the Invention
The invention relates generally to a dual port memory comprising two input/output ports, and more particularly to a dual port memory such as one used in data transmission between two microprocessor systems.
2. Description of the Background Technology
FIG. 1 is a block diagram showing a general utilization configuration of a dual port memory. In the figure, a dual port memory 1 has two input/output ports (one is called A port, while the other is called B port hereinafter). A port is connected to an A system 3 via a system bus 2. B port is connected to a B system 5 via a system bus 4. The A system 3 and B system 5 may be any type of system that processes data. For example, in many cases, it is a microprocessor system that includes a CPU. The dual port memory 1 comprises an internal memory means. This memory means is capable of being accessed separately by A system 3 and B system 5.
The above dual port memory 1 is often used for data reception/transmission between A system 3 and B system 5. For example, where A system 3 and B system 5 operate asynchronously, it is difficult to perform data transmission directly between each system. By transmitting data via dual port memory 1, it is possible for each system to input/output data when necessary. Consequently, the throughput of the system will improve. Furthermore, the systems 3 and 5 operate together to allow for the development of a larger system.
There are two conventional access methods for the dual port memory, as will be described hereinafter.
FIG. 2A shows the first access method, in which an address data applied to A port from a CPU 6 of the A system (hereinafter called A port address data) and an address data applied to B port from a CPU 7 of the B system (hereinafter called B port address data) are multiplexed by an address multiplexer 8 to be applied to a decoder 9. The decoder 9 selects one memory cell of a memory cell array 10, in accordance with either A port address data or B port address, applied via address multiplexer 8. The memory cell array 10 has a plurality of memory cells arranged in a matrix manner along the row and column directions. Each row of memory cell 11 has one word line 12 arranged as shown in FIG. 2B. Also, each column of memory cell 11 has one bit line 13. A sense amplifier 14 is dividedly arranged by each bit line 13. Through this divided sense amplifier 14, write data is applied to bit line 13 from CPU 6 or 7, or data read out into bit line 13 is provided to CPU 6 or 7. The decoder 9 selectively activates one of the plurality of word lines 12 in accordance with the applied data. This causes a transfer gate transistor 15 of the selected row to attain a conductive state. Also, decoder 9 selectively enables one of the divided sense amplifiers 14 in accordance with the applied data. This causes the selected memory cell 11 to be connected to CPU 6 or 7 via the corresponding transfer gate transistor 15. As a result, the reading and writing of data, with respect to the selected memory cell 11, is possible.
The second access method is shown in FIG. 3A. A decoder 9a and a sense amplifier 14a for A port, and a decoder 9b and a sense amplifier 14b for B port are associated with a memory cell array 100. The A port address data from CPU 6 is applied to decoder 9a, while B port address data from CPU 7 is applied to decoder 9b. The memory cell array 100 has a plurality of memory cell arranged in a matrix manner along the row and column directions, similar to the memory cell array 10 of FIG. 2A. It should be noted that memory cell array 100 has two word lines 12a and 12b arranged for each row of memory cell 11, and also two bit lines 13a and 13b arranged for each column, as shown in FIG. 3B. Also, two transfer gate transistors 15a and 15b are provided for one memory cell 11. Word line 12a, bit line 13a, and transfer gate transistor 15a are associated with A port. Word line 12b, bit line 13b, and transfer gate transistor 15b are associated with B port. Thus, CPUs 6 and 7 can access, memory cell array 100 at the same time, because the dual port memory of FIG. 3A has the access systems of A port and B port in complete independence.
Since the dual port memory of FIG. 3A is capable of being accessed by CPUs 6 and 7 simultaneously, there will be some cases where access contention from both CPUs 6 and 7 occurs, with respect to the same memory cell. On such an occasion, the state as shown in FIG. 4 occurs in accordance with the type of access from CPUs 6 and 7. First, when read access contention occurs with respect to the same memory cell (the case of FIG. 4 (1)), the data read out from the selected memory cell is
normal Next, when read access and write access contention occurs with respect to the same memory cell (the cases of FIG. 4 (2), (3)), the data read out from the selected memory cell is indefinite (that is to say, whether normal or abnormal, the data cannot be identified), while the data written into the selected memory cell is normal. When contention of write access operation occurs with respect to the same memory cell (the case of FIG. 4 (4)), the data written into the selected memory cell is indefinite.
To solve the above access contention problems, an access contention arbitrating circuit, described hereinafter, was proposed to be provided internally or externally of the dual port memory. When access contention from the systems occurs, the access arbitrating circuit grants an access right to one of the systems, according to a predetermined priority, and temporary halts the access from the other systems. Afterwards, the temporarily halted access is started when a non-contention state is achieved.
FIG. 5 is a system configuration diagram of a dual port RAM incorporating an access arbitrating circuit such as the one disclosed in Japanese Patent Laying-Open No. 62-175992.
The dual port RAM, of FIG. 5 has an output data control circuit 20, and D type flipflops 21a and 21b provided as the access arbitrating circuit. The remaining structure is similar to that of the dual port memory of FIG. 3A, with the same reference numerals being used for the corresponding portions. The output data control circuit 20 is supplied with A port address data A(A) from CPU 6, B port address data A(B) from CPU 7, A port write signal WE (A), and B port write signal WE (B). The output data control circuit 20 generates output data control signals .phi.A and .phi.B in accordance with the applied address data and write signals. Output data control signal .phi.A is applied to D flipflop 21a. Output data control signal .phi.B is applied to D type flipflop 21b. D type flipflop 21a fetches and holds A port output data Dout (A), applied from sense amplifier 14a in response to output data control signal .phi.A. The Q output of D type flipflop 21a is applied to CPU 6 as A port external output data Dout (A)*. D type flipflop 21b fetches and holds B port output data Dout (B) from sense amplifier 14b, in response to output data control signal .phi.B. The Q output of D flipflop 21b is applied to CPU 7 as B port external output data Dout (B)*.
FIG. 6 shows a further detail of the output data control circuit 20 of FIG. 5. The output data control circuit 20 comprises exclusive logical sum gates 22.sub.0 -22.sub.n, OR gate 23, and NOR gates 24a, 24b. The exclusive logical sum gates 22.sub.0 -22.sub.n each detects whether the logic of each address signals A0 (A)-An (a) included in A port address data A (A) coincides with the logic of
each address signal A0 (B)-An (B) included in B port address data A (B). OR gate 23 detects whether A port address data A (A) coincides with B port address data A (B) as a whole, by taking the logical sum of the outputs of exclusive logical sum gates 22.sub.0 -22.sub.n. NOR gate 24a receives the output of OR gate 23 and B port write signal WE (B) to generate an output data control signal .phi.A for A port. NOR gate 24b receives the output of OR gate 23 and A port write signal WE (A) to generate an output data control signal .phi.B for B port.
FIG. 7 shows the detailed structure of the D type flipflop 21b of FIG. 5. D type flipflop 21b comprises an inverter 25, and NOR gates 26-29. NOR gates 28 and 29 form the data holding circuit, with each output thereof applied to one input end of the other NOR gates 29 or 28. B port output data Dout (B) from sense amplifier 14 is applied to one input end of NOR gate 26, as well as to one input end of NOR gate 27 via inverter 25. The output data control signal .phi.B from output data control circuit 20 is applied to each other input end of NOR gates 26 and 27. Each of the outputs of NOR gates 26 and 27 are applied to the other input end of NOR gates 28 and 29. NOR gates 26 and 27 determine whether to update the data held in the data holding circuit formed by NOR gates 28 and 29, in response to output data control signal .phi.B.
The structure of D type flipflop 21a is similar to that of the above mentioned D type flipflop 21b, except that the input signal and the output signal are different to those of the above mentioned D type flipflop 21b.
FIG. 8 shows the operation in the case of contention between write access of the A port side and read access of the B port side with respect to the same memory cell, in the conventional dual port RAM shown in FIGS. 5-7. The operation at the time of access contention in the above mentioned dual port RAM is described in reference to the timing chart of FIG. 8.
First, the coincidence of A ports address A (A) with B port address A (B) is detected by exclusive logical sum gates 22.sub.0 -22.sub.n, OR gate 23. This causes the output of OR gate 23 to attain the L level. Upon the start of write operation of the A port side, A port write signal WE (A) is brought to the L level, to turn output data control signal .phi.B to the H level in response thereto. As a result, D type flipflop 21b has the update operation of the holding data inhibited. Therefore, even though the stored data of the selected memory cell is overwritten by the write operation of the A port side, D type flipflop 21b continues to hold the old data (the data before update). Accordingly, external output data Dout (B) * of B port is held steady. Afterwards, when the write operation of the A port side terminates, A port write signal WE (A) is turned to the H level, with output data control signal .phi.B brought to the L level in response thereto. This cancels the inhibition of data update in D type flipflop 21b. Therefore, the holding data of D type flipflop 21b is updated by the output data Dout (B) of B port. That is to say, external output data Dout (B) * of B port is updated to a new data at this time.
In the dual port RAM of FIGS. 5-7, external output data Dout (B) * of B port is updated to a new data (the data newly written into the memory cell) after the termination of write operation of A port, when contention between write of the A port side and read access of the B port side occurs with respect to the same memory cell. Therefore, B system must queue for the fetching of the new data until the write access of A system is terminated. In general, when access contention occurs, a BUSY signal is sent to A system or B system from dual port RAM to hold the access operation of A system or B system on standby. (This is not disclosed in Japanese Patent Laying-Open No. 62-175992). In FIG. 8, the access operation of B system responds to a BUSY signal supplied from B port to be held on standby until the write operation of A system ends. FIG. 9 is a system structure diagram of a conventional multiport memory incorporating an access contention arbitrating circuit such as Japanese Patent Laying-Open No. 63-183678. A multiport memory 34 has three input/output ports, A port, B port, and C port, so that access is possible from three CPUs 31, 32 and 33 simultaneously. In multiport memory 34, address latches 35a, 35b, and 35c latch the address data provided from CPUs 31, 32, and 33, respectively. An address selector 36 selects the address data to be applied to a memory portion 37 from the address data held in address latches 35a-35c. Write data latches 38a, 38b, and 38c latch the write data provided from CPUs 31, 32, and 33, respectively. The write data latched by write data latches 38a, 38b, and 38c are provided to memory portion 37 via write data drivers 39a, 39b, and 39c, respectively. The data read out from memory portion 37 are provided to CPUs 31, 32 and 33 via data ports 40a, 40b, and 40c, respectively. A memory control portion 41 controls address latches 35a-35c, write data latches 38a-38c, data write drivers 39a-39c, data ports 40a-40c, and memory portion 37.
The operation of the conventional multiport memory of FIG. 9 will be explained. When access contention occurs from a plurality of CPUs, memory control portion 41 holds address data and write data in each of latches 35a-35c, 38a-38c, and performs write operation into memory portion 37 after the completion of the other access.
In the multiport memory of FIG. 9, if write access occurs successively from a CPU where a write access is already waiting in the multiport memory, the write access of that CPU will wait at the CPU side.
The aforementioned access arbitrating circuit used in conventional dual port memories or multiport memories may queue the access operation with respect to the system when access contention rises between systems. This results in a disadvantage, whereby the conventional dual port memory could be used only if a function that can cope with the access standby request from the dual port memory (a READY function for example) is provided. Another problem is that the application is limited to the industrial field where some standby time is allowed.
In a system where real time processing is always performed, operation must be realized at identical timing by all means. In such a system, if the timing of standby generation is not known, a dual port memory allowing the generation of such standby time could not be used, no matter how short the standby time.
Furthermore, microcomputers used in small size systems sometimes had a READY terminal (the terminal where standby request signal is applied) deleted, because an increase in the number of LSI terminals leads to increase in cost. In such a system, a dual port memory could not be used, even though it is effective for improving the throughput of the system.